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19-3446; Rev 3; 1/07
KIT ATION EVALU ABLE AVAIL
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
General Description
The MAX5873 is an advanced 12-bit, 200Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and 1.8V supplies, this dual DAC offers exceptional dynamic performance such as 78dBc spurious-free dynamic range (SFDR) at fOUT = 16MHz and supports update rates of 200Msps, with a power dissipation of only 255mW. The MAX5873 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1VP-P to 1VP-P differential output voltage swing. The MAX5873 features an integrated 1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy. The digital and clock inputs of the MAX5873 accept 3.3V CMOS voltage levels. The MAX5873 features a flexible input data bus that allows for dual-port input or a single-interleaved data port. The MAX5873 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40C to +85C). Refer to the MAX5874 and MAX5875 data sheets for pin-compatible 14-bit and 16-bit versions of the MAX5873, respectively. Refer to the MAX5876 for an LVDS-compatible version of the MAX5873.
Features
200Msps Output Update Rate Noise Spectral Density = -152dBFS/Hz at fOUT = 16MHz Excellent SFDR and IMD Performance SFDR = 78dBc at fOUT = 16MHz (to Nyquist) SFDR = 73dBc at fOUT = 80MHz (to Nyquist) IMD = -85dBc at fOUT = 10MHz IMD = -74dBc at fOUT = 80MHz ACLR = 74dB at fOUT = 61MHz 2mA to 20mA Full-Scale Output Current CMOS-Compatible Digital and Clock Inputs On-Chip 1.2V Bandgap Reference Low 255mW Power Dissipation 68-Lead QFN-EP Package Evaluation Kit Available (MAX5873EVKIT)
MAX5873
Ordering Information
PART MAX5873EGK-D MAX5873EGK+D TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 68 QFN-EP* 68 QFN-EP* PKG CODE G6800-4 G6800-4
*EP = Exposed pad. + Denotes lead-free package. D = Dry pack.
Pin Configuration
TOP VIEW
DVDD1.8 N.C. N.C. N.C. N.C. A10 A11 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4
Applications
Base Stations: Single-Carrier UMTS, CDMA, GSM Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave Direct Digital Synthesis (DDS) Cable Modem Termination System (CMTS) Automated Test Equipment (ATE) Instrumentation
A4 A3 A2 A1 A0 N.C. N.C. N.C. N.C. GND DVDD3.3 GND GND AVDD3.3 GND REFIO FSADJ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
68
67 66 65 64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49 48 47 46 45 44
B5 B6 B7 B8 B9 B10 B11 SELIQ GND XOR DORI PD TORB CLKP CLKN GND AVCLK
Selector Guide
PART MAX5873 MAX5874 MAX5875 MAX5876 MAX5877 MAX5878 RESOLUTION (BITS) 12 14 16 12 14 16 UPDATE RATE (Msps) 200 200 200 250 250 250 LOGIC INPUTS CMOS CMOS CMOS LVDS LVDS LVDS
MAX5873
43 42 41 40 39 38 37 36 35
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
AVDD1.8
GND
OUTQN
OUTQP
GND
GND
OUTIN
DACREF
OUTIP
GND
AVDD3.3
AVDD3.3
GND
AVDD3.3
AVDD3.3
GND
QFN
________________________________________________________________ Maxim Integrated Products
AVDD1.8
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
ABSOLUTE MAXIMUM RATINGS
AVDD1.8, DVDD1.8 to GND, DACREF ................. -0.3V to +2.16V AVDD3.3, DVDD3.3, AVCLK to GND, DACREF ....... -0.3V to +3.9V REFIO, FSADJ to GND, DACREF ........-0.3V to (AVDD3.3 + 0.3V) OUTIP, OUTIN, OUTQP, OUTQN to GND, DACREF .................................-1V to (AVDD3.3 + 0.3V) CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V) A11/B11-A0/B0, XOR, SELIQ to GND, DACREF ...................................-0.3V to (DVDD3.3 + 0.3V) TORB, DORI, PD to GND, DACREF........-0.3V to (DVDD3.3 + 0.3 Continuous Power Dissipation (TA = +70C) 68-Pin QFN-EP (derate 41.7mW/C above +70C) (Note 1) ...........3333.3mW Thermal Resistance JA (Note 1)...................................+24C/W Operating Temperature Range ......................... -40C to +85C Junction Temperature .................................................... +150C Storage Temperature Range ........................... -60C to +150C Lead Temperature (soldering, 10s) ............................... +300C
Note 1: Themal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, fCLK = fDAC, external reference VREFIO = 1.25V, output load 50 double terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Drift Tempco Full-Scale Gain Error Gain-Drift Tempco Full-Scale Output Current Output Compliance Output Resistance Output Capacitance DYNAMIC PERFORMANCE Clock Frequency Output Update Rate Noise Spectral Density fCLK fDAC fDAC = fCLK / 2, single-port mode fDAC = fCLK, dual-port mode fDAC = 150MHz fDAC = 200MHz fOUT = 16MHz, -12dBFS fOUT = 80MHz, -12dBFS 1 1 1 -152 -153 200 100 200 MHz Msps dBFS/ Hz ROUT COUT IOUT GEFS External reference Internal reference External reference (Note 3) Single-ended 2 -0.5 1 5 INL DNL OS Measured differentially Measured differentially -0.025 12 0.2 0.13 0.001 10 1 100 50 20 +1.1 +0.025 Bits LSB LSB %FS ppm/C %FS ppm/C mA V M pF SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, fCLK = fDAC, external reference VREFIO = 1.25V, output load 50 double terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS fOUT = 1MHz, 0dBFS fOUT = 1MHz, -6dBFS fDAC = 100MHz fOUT = 1MHz, -12dBFS fOUT = 10MHz, -12dBFS Spurious-Free Dynamic Range to Nyquist fOUT = 30MHz, -12dBFS SFDR fOUT = 10MHz, -12dBFS fOUT = 16MHz, -12dBFS, TA +25oC fOUT = 16MHz, -12dBFS fOUT = 50MHz, -12dBFS fOUT = 80MHz, -12dBFS Spurious-Free Dynamic Range, 25MHz Bandwidth SFDR fDAC = 150MHz fDAC = 100MHz Two-Tone IMD TTIMD fDAC = 200MHz Four-Tone IMD, 1MHz Frequency Spacing, GSM Model Adjacent Channel Leakage Power Ratio 3.84MHz Bandwidth, W-CDMA Model Output Bandwidth INTER-DAC CHARACTERISTICS Gain Matching Gain-Matching Tempco Phase Matching Phase-Matching Tempco Channel-to-Channel Crosstalk REFERENCE Internal Reference Voltage Range Reference Input Compliance Range Reference Input Resistance Reference Voltage Drift VREFIO VREFIOCR RREFIO TCOREF 1.14 0.125 10 25 1.2 1.26 1.250 V V k ppm/C Gain Gain/C Phase Phase/C fCLK = 200MHz, fOUT = 50MHz, 0dBFS fOUT = 60MHz fOUT = DC - 80MHz fOUT = DC 0.2 +0.01 20 0.25 0.002 -70 dB ppm/C Degrees Degrees/ C dB FTIMD fDAC = 150MHz fDAC = 184.32MHz (Note 4) fOUT = 16MHz, -12dBFS fOUT1 = 9MHz, -7dBFS; fOUT2 = 10MHz, -7dBFS fOUT1 = 79MHz, -7dBFS; fOUT2 = 80MHz, -7dBFS fOUT = 16MHz, -12dBFS 72 68 MIN TYP 86 82 80 85 80 80 78 78 77 73 85 -85 dBc -74 -82 dBc dBc dBc MAX UNITS
MAX5873
fDAC = 200MHz
ACLR BW-1dB
fOUT = 61.44MHz
74 240
dB MHz
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3
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, fCLK = fDAC, external reference VREFIO = 1.25V, output load 50 double terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Output Fall Time Output Rise Time Output-Voltage Settling Time Output Propagation Delay Glitch Impulse Output Noise TIMING CHARACTERISTICS Data to Clock Setup Time Data to Clock Hold Time Single-Port (Interleaved Mode) Data Latency Dual-Port (Parallel Mode) Data Latency Minimum Clock Pulse-Width High Minimum Clock Pulse-Width Low tCH tCL CLKP, CLKN CLKP, CLKN 0.7 x DVDD3.3 0.3 x DVDD3.3 1 VPD = VTORB = VDORI = 3.3V CIN Sine wave Square wave SRCLK VCOM RCLK CCLK AVDD3.3 AVDD1.8 3.135 1.710 (Note 7) 1.5 2.5 > 1.5 > 0.5 > 100 AVCLK / 2 0.3 5 2.5 3.3 1.8 3.465 1.890 20 tSETUP tHOLD Referenced to rising edge of clock (Note 6) Referenced to rising edge of clock (Note 6) Latency to I output Latency to Q output -0.6 2.1 -1.2 1.5 9 8 5.5 2.4 2.4 ns ns Clock cycles Clock cycles ns ns NOUT SYMBOL tFALL tRISE tSETTLE tPD CONDITIONS 90% to 10% (Note 5) 10 % to 90% (Note 5) Output settles to 0.025% FS (Note 5) Excluding data latency (Note 5) Measured differentially IOUTFS = 2mA IOUTFS = 20mA MIN TYP 0.7 0.7 14 1.1 1 30 30 MAX UNITS ns ns ns ns pV*s pA/Hz
ANALOG OUTPUT TIMING (See Figure 4)
CMOS LOGIC INPUTS (A11/B11-A0/B0, XOR, SELIQ, PD, TORB, DORI) Input Logic High Input Logic Low Input Leakage Current PD, TORB, DORI Internal Pulldown Resistance Input Capacitance CLOCK INPUTS (CLKP, CLKN) Differential Input Voltage Swing Differential Input Slew Rate External Common-Mode Voltage Range Input Resistance Input Capacitance POWER SUPPLIES Analog Supply Voltage Range V VP-P V/s V k pF VIH VIL IIN V V A M pF
4
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, GND = 0, fCLK = fDAC, external reference VREFIO = 1.25V, output load 50 double terminated, transformer-coupled output, IOUTFS = 20mA, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER Digital Supply Voltage Range Clock Supply Voltage Range Analog Supply Current SYMBOL DVDD3.3 DVDD1.8 AVCLK IAVDD3.3 + IAVCLK IAVDD1.8 IDVDD3.3 IDVDD1.8 Power Dissipation Power-Supply Rejection Ratio PDISS PSRR fDAC = 200Msps, fOUT = 1MHz Power-down fDAC = 200Msps, fOUT = 1MHz Power-down fDAC = 200Msps, fOUT = 1MHz Power-down fDAC = 200Msps, fOUT = 1MHz Power-down fDAC = 200Msps, fOUT = 1MHz Power-down AVDD3.3 = AVCLK = DVDD3.3 = +3.3V 5% (Notes 7, 8) -0.1 CONDITIONS MIN 3.135 1.710 3.135 TYP 3.3 1.8 3.3 52 0.001 24 0.001 0.5 0.001 20 0.001 255 14 +0.1 300 25 3 32 MAX 3.465 1.890 3.465 58 UNITS V V mA mA mA mA mW W %FS/V
MAX5873
Digital Supply Current
Note 2: Specifications at TA +25C are guaranteed by production testing. Specifications at TA < +25C are guaranteed by design and characterization data. Note 3: Nominal full-scale current IOUTFS = 32 x IREF. Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5873. Note 5: Parameter measured single-ended into a 50 termination resistor. Note 6: Not production tested. Guaranteed by design and characterization data. Note 7: A differential clock input slew rate of > 100V/s is required to achieve the specified dynamic performance. Note 8: Parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 50Msps)
MAX5873 toc01
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 100Msps)
MAX5873 toc02
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 150Msps)
0dBFS 80 -12dBFS 60 -6dBFS
MAX5873 toc03
100 0dBFS 80 -12dBFS SFDR (dBc) 60 -6dBFS
100 0dBFS 80 -12dBFS SFDR (dBc) 60 -6dBFS
100
40
40
SFDR (dBc) 50
40
20
20
20
0 0 5 10 15 20 25 fOUT (MHz)
0 0 10 20 30 40 fOUT (MHz)
0 0 15 30 45 60 75 fOUT (MHz)
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5
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT FREQUENCY (fCLK = 200Msps)
MAX5873 toc04
TWO-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 100Msps)
MAX5873 toc05
TWO-TONE IMD (fCLK = 100Msps)
BW = 12MHz fOUT1 = 29.9795MHz fOUT2 = 31.0049MHz fOUT1 fOUT2
MAX5873 toc06 MAX5873 toc09
100 0dBFS 80 -12dBFS -6dBFS 60
-40 -50 TWO-TONE IMD (dBc) -60 -70 -80 -90 -6dBFS -100
0
-20 OUTPUT POWER (dBFS)
SFDR (dBc)
-40
-12dBFS
40
-60 2 x fOUT1 - fOUT2 -80 2 x fOUT2 - fOUT1
20
0 0 20 40 60 80 100 fOUT (MHz)
-100 5 10 15 20 25 30 35 40 24 26 28 30 fOUT (MHz) 32 34 36 fOUT (MHz)
TWO-TONE IMD vs. OUTPUT FREQUENCY (1MHz CARRIER SPACING, fCLK = 200Msps)
MAX5873 toc07
SFDR vs. FULL-SCALE OUTPUT CURRENT (fCLK = 200MHz)
AOUT = -6dBFS 20mA 80 10mA 5mA
MAX5873 toc08
SFDR vs. TEMPERATURE (fCLK = 200MHz)
90 AOUT = -6dBFS TA = -40C TA = +25C 80 TA = +85C 75
-40 -50 TWO-TONE IMD (dBc) -60 -70 -80 -90 -6dBFS -100 0 10 20 30 40 50 60 70
100
85 SFDR (dBc) SFDR (dBc) 60 80 100 60
-12dBFS
40
20
0 80 0 20 40 fOUT (MHz) fOUT (MHz)
70 0 20 40 60 80 100 fOUT (MHz)
INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5873 toc10
DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
MAX5873 toc11
0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 0 1024 2048 3072
0.4
4096
0
1024
2048
3072
4096
DIGITAL INPUT CODE
DIGITAL INPUT CODE
6
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
Typical Operating Characteristics (continued)
(AVDD3.3 = DVDD3.3 = AVCLK = 3.3V, AVDD1.8 = DVDD1.8 = 1.8V, external reference, VREFIO = 1.25V, RL = 50 double-terminated, IOUTFS = 20mA, TA = +25C, unless otherwise noted.)
POWER DISSIPATION vs. CLOCK FREQUENCY (fOUT = 10MHz)
MAX5873 toc12
MAX5873
POWER DISSIPATION vs. SUPPLY VOLTAGE (fCLK = 100MHz, fOUT = 10MHz)
AOUT = 0dBFS
MAX5873 toc13
280
AOUT = 0dBFS
250
POWER DISSIPATION (mW)
240
POWER DISSIPATION (mW)
260
240
230
EXTERNAL REFERENCE
220
220
200
210
INTERNAL REFERENCE
180 30 50 70 90 110 130 150 170 190 fCLK (MHz)
200 3.135
3.235
3.335
3.435
SUPPLY VOLTAGE (V)
FOUR-TONE POWER RATIO PLOT (fCLK = 150MHz, fCENTER = 31.6040MHz)
MAX5873 toc14
ACLR FOR WCDMA MODULATION, TWO CARRIERS
-30 ANALOG OUTPUT POWER (dBm) -40 -50 -60 -70 -80 -90 -100 -110 fCLK = 184.32MHz fCENTER = 30.72MHz ACLR = 71.20dB
MAX5873 toc15
0 fOUT1 -20 OUTPUT POWER (dBFS) fOUT2 fOUT3 fOUT4
-20
-40 BW = 12MHz -60
-80
-100 26 28 30 32 fOUT (MHz) fOUT1 = 29.6997MHz fOUT3 = 32.4829MHz fOUT2 = 30.7251MHz fOUT4 = 34.0210MHz 34 36 38
-120 3.05MHz/div
ACLR FOR WCDMA MODULATION, SINGLE CARRIER
-30 ANALOG OUTPUT POWER (dBm) -40 -50 ACLR (dB) -60 -70 -80 -90 -100 -110 -120 DC 9.2MHz/div 92.16MHz 60 1 65 75 76.9 fCENTER = 30.72MHz fCLK = 184.32MHz ACLR = 76dB
MAX5873 toc16
WCDMA BASEBAND ACLR
ADJACENT ALTERNATE 80 79.0 76.8 78.3 76.7 77.6
MAX5873 toc17
85
75.7 76.4
70
2
3
4
NUMBER OF CARRIERS
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7
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
Pin Description
PIN 1-5 6-9, 57-60 10, 12, 13, 15, 20, 23, 26, 27, 30, 33, 36, 43 11 14, 21, 22, 31, 32 16 17 18 19, 34 24 25 28 29 35 37 38 NAME A4, A3, A2, A1, A0 N.C. GND FUNCTION Data Bits A4-A0. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits are not used. Connect bits A4-A0 to GND in single-port mode. No Connection. Leave floating or connect to GND. Converter Ground Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to GND. Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with a 0.1F capacitor to GND. Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F capacitor to GND. REFIO can be driven with an external reference source. See Table 1. Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2k resistor between FSADJ and DACREF. See Table 1. Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2k resistor between FSADJ and DACREF. Internally connected to GND. Do not use as a ground connection. Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a 0.1F capacitor to GND. Complementary Q-DAC Output. Negative terminal for current output. Q-DAC Output. Positive terminal for current output. Complementary I-DAC Output. Negative terminal for current output. I-DAC Output. Positive terminal for current output. Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F capacitor to GND. Complementary Converter Clock Input. Negative input terminal for differential converter clock. Internally biased to AVCLK / 2. Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to AVCLK / 2. Two's-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two'scomplement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format. TORB has an internal pulldown resistor. Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for normal operation. PD has an internal pulldown resistor. Dual (Parallel)/Single (Interleaved) Port Select Input. Set DORI high to configure as a dual-port DAC. Set DORI low to configure as a single interleaved-port DAC. DORI has an internal pulldown resistor.
DVDD3.3 AVDD3.3 REFIO FSADJ DACREF AVDD1.8 OUTQN OUTQP OUTIN OUTIP AVCLK CLKN CLKP
39
TORB
40
PD
41
DORI
8
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
Pin Description (continued)
PIN 42 NAME XOR FUNCTION DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND. DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ's logic state is only valid in single-port (interleaved) mode. Data Bits B11-B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state of SELIQ determines where the data bits are directed. Digital Supply Voltage. Accepts a supply voltage range of 1.71V to 1.89V. Bypass with a 0.1F capacitor to GND.
MAX5873
44
SELIQ B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0 DVDD1.8
45-56
61 62-68 --
A11, A10, A9 Data Bits A11-A5. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits A8, A7, A6, A5 are not used. Connect bits A11-A5 to GND in single-port mode. EP Exposed Pad. Must be connected to GND through a low-impedance path.
Detailed Description
Architecture
The MAX5873 high-performance, 12-bit, dual currentsteering DAC (Figure 1) operates with DAC update rates up to 200Msps. The converter consists of input registers and a demultiplexer for single-port (interleaved) mode, followed by a current-steering array. During operation in interleaved mode, the input data registers demultiplex the single-port data bus. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal current-switching network, in combination with external 50 termination resistors, converts the differential output currents into dual differential output voltages with a 0.1V to 1V peak-to-peak output voltage range. An integrated 1.2V bandgap reference, control amplifier, and user-selectable external resistor determine the data converter's full-scale output range.
The MAX5873's reference circuit (Figure 2) employs a control amplifier to regulate the full-scale current IOUTFS for the differential current outputs of the DAC. Configured as a voltage-to-current amplifier, calculate the output current as follows: IOUTFS = 32 x VREFIO RSET 1 x 1 - 212
where I OUTFS is the full-scale output current of the DAC. R SET (located between FSADJ and DACREF) determines the amplifier's full-scale output current for the DAC. See Table 1 for a matrix of different IOUTFS and RSET selections.
Reference Architecture and Operation
The MAX5873 supports operation with the internal 1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external, lowimpedance reference source. REFIO also serves as a reference output when the DAC operates in internal reference mode. For stable operation with the internal reference, decouple REFIO to GND with a 1F capacitor. Due to its limited output drive capability, buffer REFIO with an external amplifier when driving large external loads.
Table 1. IOUTFS and RSET Selection Matrix Based on a Typical 1.200V Reference Voltage
FULL-SCALE CURRENT IOUTFS (mA) 2 5 10 15 20 RSET () CALCULATED 19.2k 7.68k 3.84k 2.56k 1.92k 1% EIA STD 19.1k 7.5k 3.83k 2.55k 1.91k
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9
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
DVDD3.3
GND
DVDD1.8
AVDD1.8
AVDD3.3 OUTIP
TORB DORI SELIQ DATA11- DATA0 XOR LATCH XOR/ DECODE LATCH LATCH DAC OUTQN AVCLK CLKP CLKN GND CLK INTERFACE DACREF 1.2V REFERENCE REFIO FSADJ CMOS RECEIVER LATCH OUTQP LATCH XOR/ DECODE LATCH LATCH DAC OUTIN
MAX5873
POWER-DOWN BLOCK
PD
GND
Figure 1. MAX5873 High-Performance, 12-Bit, Dual Current-Steering DAC
Analog Outputs (OUTIP, OUTIN, OUTQP, OUTQN)
Each MAX5873 DAC outputs two complementary currents (OUTIP/N, OUTQP/N) that operate in a singleended or differential configuration. A load resistor converts these two output currents into complementary single-ended output voltages. A transformer or a differential amplifier configuration converts the differential voltage existing between OUTIP (OUTQP) and OUTIN (OUTQN) to a single-ended voltage. If not using a transformer, the recommended termination from the output is a 25 termination resistor to ground and a 50 resistor between the outputs. To generate a single-ended output, select OUTIP (or OUTQP) as the output and connect OUTIN (or OUTQN) to GND. SFDR degrades with single-ended operation. Figure 3 displays a simplified diagram of the internal output structure of the MAX5873.
(AVCLK) to achieve the lowest possible jitter performance. Drive the differential clock inputs from a singleended or a differential clock source. For single-ended operation, drive CLKP with a logic source and bypass CLKN to GND with a 0.1F capacitor. CLKP and CLKN are internally biased to AVCLK / 2. This facilitates the AC-coupling of clock sources directly to the device without external resistors to define the DC level. The dynamic input resistance from CLKP and CLKN to ground is > 5k.
Data Timing Relationship
Figure 4 displays the timing relationship between digital CMOS data, clock, and output signals. The MAX5873 features a 1.5ns hold, a -1.2ns setup, and a 1.1ns propagation delay time. A nine (eight)-clock-cycle latency exists between CLKP/CLKN, and OUTIP/OUTIN (OUTQP/OUTQN) when operating in single-port (interleaved) mode. In dual-port (parallel) mode, the clock latency is 5.5 clock cycles for both channels.
Clock Inputs (CLKP, CLKN)
The MAX5873 features flexible differential clock inputs (CLKP, CLKN) operating from a separate supply
10
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
1.2V REFERENCE
AVDD CURRENT SOURCES CURRENT SWITCHES
10k REFIO 1F OUTIP FSADJ IREF RSET DACREF IREF = VREFIO / RSET CURRENT-SOURCE ARRAY DAC OUTIN
IOUT OUTIN OUTIP
IOUT
Figure 2. Reference Architecture, Internal Reference Configuration
Figure 3. Simplified Analog Output Structure
Table 2. DAC Output Code Table
DIGITAL INPUT CODE OFFSET BINARY 0000 0000 0000 0111 1111 1111 1111 1111 1111 TWO'S COMPLEMENT 1000 0000 0000 0000 0000 0000 0111 1111 1111 OUT_P 0 IOUTFS OUT_N IOUTFS 0
IOUTFS / 2 IOUTFS / 2
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB, DORI) The TORB input selects between two's-complement or binary digital input data. Set TORB to a CMOS-logichigh level to indicate a two's-complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format. The DORI input selects between a dual-port (parallel) or single-port (interleaved) DAC. Set DORI high to configure the MAX5873 as a dual-port DAC. Set DORI low to configure the MAX5873 as a single-port DAC. In dual-port mode, connect SELIQ to ground. CMOS DAC Inputs (A11/B11-A0/B0, XOR, SELIQ) The MAX5873 latches input data on the rising edge of the clock in a user-selectable two's-complement or binary format. A logic-high voltage on TORB selects two'scomplement and a logic-low selects offset binary format. The MAX5873 includes a single-ended, CMOS-compatible XOR input. Input data (all bits) are compared with the
bit applied to XOR through exclusive-OR gates. Pulling XOR high inverts the input data. Pulling XOR low leaves the input data noninverted. By applying a previously encoded pseudo-random bit stream to the data input and applying decoding to XOR, the digital input data can be decorrelated from the DAC output, allowing for the troubleshooting of possible spurious or harmonic distortion degradation due to digital feedthrough on the printed circuit board (PCB). A11/B11-A0/B0, XOR, and SELIQ are latched on the rising edge of the clock. In single-port mode (DORI pulled low) a logic-high signal on SELIQ directs the B11-B0 data onto the I-DAC inputs. A logic-low signal at SELIQ directs data to the Q-DAC inputs. In dual-port (parallel) mode (DORI pulled high), data on pins A11-A0 are directed onto the Q-DAC inputs and B11-B0 are directed onto the I-DAC inputs. Power-Down Operation (PD) The MAX5873 also features an active-high power-down mode that reduces the DAC's digital current consumption from 21.5mA to less than 2A and the analog current consumption from 76mA to less than 2A. Set PD high to power down the MAX5873. Set PD low for normal operation. When powered down, the MAX5873 reduces the overall power consumption to less than 14W. The MAX5873 requires 10ms to wake up from power-down and enter a fully operational state. The PD integrated pulldown resistor activates the MAX5873 if PD is left floating.
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
DATA11-DATA0, XOR N-1 N N+1 N+2
tS
tH
CLK tPD DAC OUTPUT N-6 N-5 N-4 N-3
N-2
(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM
CLK
DATAIN
I0
Q0
I1
Q1
I2
Q2
I3
Q3
SELIQ tS tH I-5 I OUT I-6 I-4 I-3 I-2
Q OUT
Q-6 tPD
Q-5 Q-4 Q-3 (b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM Q-2
Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode
Applications Information
CLK Interface
The MAX5873 features a flexible differential clock input (CLKP, CLKN) with a separate supply (AV CLK ) to achieve optimum jitter performance. Use an ultra-low jitter clock to achieve the required noise density. Clock jitter must be less than 0.5psRMS for meeting the specified noise density. For that reason, the CLKP/CLKN input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Differential
12
clock drive is required to achieve the best dynamic performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass CLKN to GND with a 0.1F capacitor. Figure 5 shows a convenient and quick way to apply a differential signal created from a single-ended source (e.g., HP/Agilent 8644B signal generator) and a wideband transformer. Alternatively, these inputs can be driven from a CMOS-compatible clock source; however, it is recommended to use sinewave or AC-coupled differential ECL/PECL drive for best dynamic performance.
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
WIDEBAND RF TRANSFORMER PERFORMS SINGLE-ENDED-TODIFFERENTIAL CONVERSION 25 SINGLE-ENDED CLOCK SOURCE 1:1 25 0.1F CLKN TO DAC 0.1F CLKP
mended since additional noise and distortion will be added. The distortion performance of the DAC depends on the load impedance. The MAX5873 is optimized for 50 differential double termination. It can be used with a transformer output as shown in Figure 6 or just one 25 resistor from each output to ground and one 50 resistor between the outputs (Figure 7). This produces a fullscale output power of up to -2dBm, depending on the output current setting. Higher termination impedance can be used at the cost of degraded distortion performance and increased output noise voltage.
MAX5873
GND
Grounding, Bypassing, and PowerSupply Considerations
Grounding and power-supply decoupling can strongly influence the MAX5873 performance. Unwanted digital crosstalk couples through the input, reference, power supply, and ground connections, and affects dynamic performance. High-speed, high-frequency applications require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and internal crosstalk that can significantly affect the MAX5873 dynamic performance. Use a multilayer PCB with separate ground and powersupply planes. Run high-speed signals on lines directly above the ground plane. Keep digital signals as far away from sensitive analog inputs and outputs, reference input sense lines, common-mode input, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the DAC's dynamic performance. Keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches.
Figure 5. Differential Clock-Signal Generation
Differential Coupling Using a Wideband RF Transformer
Use a pair of transformers (Figure 6) or a differential amplifier configuration to convert the differential voltage existing between OUTIP/OUTQP and OUTIN/OUTQN to a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output to limit the output power to < 0dBm full scale. Pay close attention to the transformer core saturation characteristics when selecting a transformer for the MAX5873. Transformer core saturation can introduce strong 2nd-order harmonic distortion especially at low output frequencies and high signal amplitudes. For best results, center tap the transformer to ground. When not using a transformer, terminate each DAC output to ground with a 25 resistor. Additionally, place a 50 resistor between the outputs (Figure 7). For a single-ended unipolar output, select OUTIP (OUTQP) as the output and ground OUTIN (OUTQN) to GND. Driving the MAX5873 single-ended is not recom-
50 DATA11-DATA0 OUTIP/OUTQP 100 T2, 1:1
VOUT, SINGLE-ENDED
MAX5873
12 OUTIN/OUTQN
T1, 1:1 50
GND
WIDEBAND RF TRANSFORMER T2 PERFORMS THE DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
Figure 6. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer ______________________________________________________________________________________ 13
12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
menting large ground planes in the PCB design allow for the highest performance operation of the DAC. Use an array of at least 4 x 4 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 68-pin QFNEP package. Connect the MAX5873 exposed paddle to GND. Vias connect the land pattern to internal or external copper planes. Use as many vias as possible to the ground plane to minimize inductance.
25 DATA11-DATA0 OUTIP/OUTQP 50 OUTN 25 GND OUTP
MAX5873
12 OUTIN/OUTQN
Static Performance Parameter Definitions
Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees a monotonic transfer function. Offset Error The offset error is the difference between the ideal and the actual offset current. For a DAC, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the DAC. This error affects all codes by the same amount.
Figure 7. Differential Output Configuration
The MAX5873 requires five separate power-supply inputs for analog (AVDD1.8 and AVDD3.3), digital (DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry. Decouple each AVDD, DVDD, and AVCLK input pin with a separate 0.1F capacitor as close to the device as possible with the shortest possible connection to the ground plane (Figure 8). Minimize the analog and digital load capacitances for optimized operation. Decouple all three power-supply voltages at the point they enter the PCB with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. The analog and digital power-supply inputs AVDD3.3, AVCLK, and DVDD3.3 allow a 3.135V to 3.465V supply voltage range. The analog and digital power-supply inputs AVDD1.8 and DVDD1.8 allow a 1.71V to 1.89V supply voltage range. The MAX5873 is packaged in a 68-pin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and optimized DAC AC performance. The EP enables the use of necessary grounding techniques to ensure highest performance operation. Thermal efficiency is not the key factor, since the MAX5873 features low-power operation. The exposed pad ensures a solid ground connection between the DAC and the PCB's ground layer. The data converter die attaches to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PCB side of the package. This allows for a solid attachment of the package to the PCB with standard infrared reflow (IR) soldering techniques. A specially created land pattern on the PCB, matching the size of the EP (6mm x 6mm), ensures the proper attachment and grounding of the DAC. Refer to the MAX5873 EV kit data sheet. Designing vias into the land area and imple14
BYPASSING--DAC LEVEL AVDD1.8 AVDD3.3 AVCLK
0.1F
0.1F
0.1F
DATA11-DATA0
OUTIP/OUTQP
MAX5873
12 OUTIN/OUTQN
0.1F
0.1F
DVDD1.8
DVDD3.3
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 8. Recommended Power-Supply Decoupling and Bypassing Circuitry
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs
Gain Error A gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. Two-Tone Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in dBc (or dBFS) of the worst 3rd-order (or higher) IMD product(s) to either output tone. Adjacent Channel Leakage Power Ratio (ACLR) Commonly used in combination with wideband codedivision multiple-access (W-CDMA), ACLR reflects the leakage power ratio in dB between the measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited RF signal passes through a nonlinear device. Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles its new output value to within the converter's specified accuracy. Glitch Impulse A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV*s.
MAX5873
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum can be derived from the DAC's resolution (N bits): SNR = 6.02 x N + 1.76 However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading; therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset. Noise Spectral Density The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and shot noise). Noise spectral density is the noise power in 1Hz bandwidth, specified in dBFS/Hz. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of their next-largest distortion component. SFDR is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC's fullscale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist.
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12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs MAX5873
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM 1 C 21-0122 2
Revision History
Pages changed at Rev 3: 1-16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
68L QFN.EPS

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